Cladded silver and silver alloy metallization for improved adhesion and electromigration resistance

ABSTRACT

In semiconductor integrated circuit and device fabrication interconnect metallization is accomplished by a clad Ag deposited on a SiO2 level on a Si surface. The clad Ag has a layer of an alloy of Ag and Al (5 atomic %) contacting the SiO2, a layer of substantially pure Ag and an outer layer of the Ag and Al alloy. The alloy improves adhesion to the SiO2, avoids agglomeration of the Ag, reduces or eliminates diffusion at the SiO2 surface, reduces electromigration and presents a passive exterior surface.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from the U.S. provisional patent application Ser. No. 60/602,762 filed on Aug. 18, 2004 in the name of Terry L. Alford and Ekta Misra entitled “Cladded Silver and Silver Alloy Metallization for Improved Adhesion and Electromigration Resistance” incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to conductive interconnects for integrated circuits and more particularly to deposited silver (Ag) interconnects clad in a deposited silver-aluminum (Ag (Al)) alloy.

BACKGROUND

Continuous shrinkage in device dimensions in ultra-large-scale-integration (ULSI) technologies has resulted in interconnects being subjected to high current densities and thermal stresses leading to their premature failure. Electromigration is one of the governing phenomenon which contributes to early failure of interconnects. Choices of metallization is an important parameter that affects the performance of chip interconnects. Until recently, Al was considered as the ideal interconnect metallization, but its relatively high resistivity (˜2.7 μΩ-cm) and poor electromigration resistance have led to an ongoing search for a better replacement. Ag is one of the potential interconnect materials and has excellent electromigration resistance. However, Ag tends to agglomerate at higher temperatures, and does not adhere too well to dielectrics due to its inert nature when in contact with most materials.

The closest art is believed to be PCT application Serial No. PCT/US04/028705 entitled “Thermal Stability for Silver Metallization,” of Kim and Alford, filed Sep. 2, 2004, claiming priority from U.S. provisional patent application Ser. No. 60/499,645. Both applications are incorporated herein by reference. Like the provisional application, the PCT application mainly deals with the thermal stability of Ag(Al) alloy thin films on SiO₂ in terms of prevention of agglomeration and improvement of adhesion between the metallization and the substrate. The present invention, however, deals with a cladded Ag metallization structure.

BRIEF SUMMARY

In accordance with the present invention interconnects for integrated circuits, components and devices of substantially pure Ag are clad in an Ag (Al) alloy. Preferably, in an exemplary embodiment, an Ag (Al) alloy is deposited on a semiconductor oxide layer to a thickness of from about 6 nm to 12 nm, and preferably from about 8 nm to about 10 nm. A layer of substantially pure Ag is then deposited on the thin alloy film. A further thin film of the Ag (Al) is then deposited over the Ag to a thickness of preferably from about 3 nm to about 10 nm and more preferably from about 4 nm to about 6 nm. The alloy in accordance with the preferred exemplary embodiment has Al content in a range from about 0.5 atomic % to about 5 atomic % and more preferably in a range from greater than about 0.5 atomic % to about 2 atomic %, the remainder of the alloy content being substantially pure Ag.

Put another way, in the preferred embodiment, the layer of alloy deposited on the oxide layer is of a thickness sufficient to create a continuous film separating the Ag from the underlying oxide. This prevents agglomeration and the alloy film on the oxide is also of a thickness so as to prevent diffusion of the silver into the oxide. The further alloy film deposited over the Ag is of a thickness so as to be a continuous film capable of passivating the Ag upper surface. In the preferred exemplary embodiment the oxide is SiO₂ grown on a Si wafer.

The clad structure is intended to alleviate problems of adhesion and agglomeration observed in pure Ag films and is put forth as a replacement for Al and Cu interconnect metallization in the microelectronics industry because of the reasons listed below:

-   -   a) Less processing steps in comparison to Cu metallization.     -   b) Lower overall resistance in comparison to both Al and Cu         metallization.     -   c) Better electromigration resistance compared to Al, Cu and         pure Ag. According to previous study the activation energies of         pure Ag (0.58 eV) and Cu (0.67 eV) metallization are similar         thus their failure times would also be similar [M. Hauder, J.         Gstottner, W. Hansch, and D. Scmitt-Landsiedel, Appl. Phys.         Lett., 78, 838 (2001)]. However, as has been shown         experimentally in this study the failure time of the clad         structure is 38 times better than that of pure Ag, thus leading         to the conclusion that the electromigration resistance of the         proposed metallization structure would also be better than that         of Cu.     -   d) No agglomeration observed at elevated temperatures.     -   e) Better adhesion to SiO₂ compared to pure Ag metallization.

This invention solves the problems of electromigration and Joule heating-induced early failure of interconnect metallization. It also alleviates problems, viz. agglomeration and poor adhesion to SiO₂ associated with pure Ag metallization.

This invention can be used as:

-   -   a) Interconnect metallization for conventional microelectronics         as well as high temperature applications.     -   b) Contacts used in organic light emitting diodes and also as         metallization in large scale (Generation II and greater)         flexible displays and flexible electronics with minimum voltage         drop at room temperatures.         As used herein “interconnects” means conductive traces, pads,         contacts or other conductive features or areas of an integrated         circuit, a component or a device, from the very smallest feature         in ULSI circuitry to the aforementioned large scale flexible         display features.

For conventional electronics, microelectronics fabrication industries can use this invention. Also fabrication companies which are still using Al as interconnect metallization can switch to the Ag and Ag alloy clad structure proposed here and forgo the difficulties of Cu processing (etching, step coverage, CMP). For high temperature electronics, automotive companies are interested in electronics for under the hood applications. The invention is useful for flexible OLED displays and flexible electronics also.

This invention will be useful for interconnect metallization used for conventional microelectronics as well as high temperature applications. The Alford group at Arizona State University previously developed a reactive ion etch process for Ag metallization. See “Novel technique to pattern silver using CF₄ and CF₄/O₂ glow discharges,” P. Nguyen, Y. Zeng, and T. L. Alford, J. Vac. Sci. Technol. B 19, 158 (2001), incorporated herein by reference. The conjunction with these two technologies will also enable smaller fabrication facilities to use current Al etch processes and extend their usefulness by not encumbering the cost of chemical mechanical polishing toolsets associated with copper metallization and the accompanying diffusion barrier technology. Moreover, the low resistivity and good adhesion properties makes this metallization compatible with the Ag contacts used in organic light emitting diodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fragmentary cross-sectional view, not to scale, of Ag interconnects clad in Ag (Al) alloy, in accordance with the invention, on a SiO₂ layer of an integrated circuit; and

FIG. 2 is a flow chart representative of the steps of formation of the Ag (Al) alloy clad Ag interconnects of FIG. 1.

DETAILED DESCRIPTION

The silver-silver alloy clad structure proposed here consists of layers of Ag (Al-5 atomic %)/Ag/(Ag(Al-5 atomic %)/SiO₂. A cross-section of such a structure is shown in FIG. 1. Silver does not adhere well to SiO₂. It undergoes agglomeration at higher temperatures (>200° C.), and it is susceptible to oxidation and sulfurization. Previous study has shown that addition of Al (5 atomic %) prevents the agglomeration of Ag at higher temperatures (>400° C.) and thus improves the adhesion of the alloy to SiO₂ See “Improvement of the thermal stability of silver metallization,” H. C. Kim, and T. L. Alford, J. Appl. Phys., 94, 5393 (2003), incorporated herein by reference.

The Ag(Al) alloy layer in contact with the oxide layer on a wafer acts as an adhesion layer between SiO₂ and the subsequent layers of metals/dielectrics. The alloy thin film on the top of the oxide acts as a cladding layer for the pure Ag and thus reduces surface diffusion and enhances the electromigration resistance of the stack structure. The electromigration behavior of the entire structure is further improved because the Ag alloy encapsulation, being harder due to solution hardening effect, produces compression stress between the Ag alloy-Ag interface thus leading to reduced hillock formation and also since most of the current flows through the Ag layer due to its comparatively lower resistivity. Thus the Joule heating effect in the clad structure is lower. The present structure, then, is based on the proposition that the use of the Ag(Al) alloy layers in such a clad structure offsets the need for extra diffusion barrier layers and also improves the overall electromigration behavior of the structure.

The Ag (Al) alloy should contain Al from about 0.5 atomic % to about 5 atomic %, the remainder of the alloy being substantially pure Ag. Preferably the percentage of aluminum in the alloy is between greater than about 0.5 atomic % to about 2 atomic %. The thickness of the thin alloy film in contact with the SiO2 can range between about 6 nm to about 12 nm, more preferably from about 8 nm to about 10 nm. A benefit of this construction is that the Ag layer thickness has no criticality and may be of any of a wide range of thicknesses. The final Ag (Al) alloy layer can have a thickness in the range from about 3 nm to about 10 nm, and more preferably is from about 4 nm to 6 nm thick.

Experimental Fabrication

The Ag(Al) alloy of a specific exemplary experimental embodiment was 5 atomic % Al. The source of the Ag(Al) alloy was prepared by forming a solid solution of 95 atomic % pure Ag slugs and 5 atomic % pure Al slugs in the electron-beam (e-beam) evaporator. Single-line test structures of 3.75 μm line widths of pure Ag, Ag(Al) alloy and Ag(Al)/Ag/Ag(Al) on SiO₂ were fabricated on (100)-oriented p-type silicon wafers with nominal resistivity between 0.2 and 0.8 Ω-cm by standard lift-off technique. The Si wafers were dipped in HF for 30 s to remove native oxide as indicated at 10 in the process flow chart of FIG. 2. Then ˜200 nm of thermal oxide was grown as indicated at 12. At this point in the formation of an integrated circuit, the SiO₂ layer would be patterned as is conventional, as indicated at 14. This then was followed by deposition of metal contacts as at 16.

Experimentally, as indicated at 18, 20 and 22, without breaking vacuum, clad structures were obtained by sequential deposition of the Ag(Al) alloy (˜10 nm), the pure Ag (˜130 nm) and the Ag(Al) alloy (˜10 nm) on the patterned oxide of the wafer using an e-beam evaporator at a base pressure of 3 ×10⁻⁶ torr and deposition pressure of 4×10⁻⁶ torr. The pure Ag and Ag(Al) alloy metal depositions were also done by known e-beam evaporation technique. The deposition environment pressure should be as near to null as possible.

Test Results

The failure time of the fabricated single line test structures was determined using a Tektronics 372 Semiconductor Workbench. In order to accelerate the failure of the structures the testing was done at elevated temperatures by placing the samples on a resistance heated hot stage. The test structures were all subjected to a constant current (0.15 A) and temperature conditions (190° C.) and their corresponding failure times were obtained. The failure criterion for the test lines was set to be complete open circuit. Table I below gives the resistivity in μΩ-cms and failure times in seconds obtained for the three different structures (Ag/SiO₂, Ag(Al)/SiO₂ and Ag(Al)/Ag/Ag/(Al)/SiO₂) under the set temperature and current conditions. TABLE I Structure Type Resistivity (μΩ-cm) Failure Time(s) Ag/SiO₂ 1.84   576 Ag(Al)/SiO₂  2.14*  3,276 Ag(Al)/Ag/Ag(Al)/SiO₂ 2.05 21,672 *Effective resistivity of the overall cladded stack structure

As observed in the Table I above, the failure time of Ag(Al)/SiO₂ structures was about six times better than that of pure Ag because the alloy does not agglomerate on the SiO₂ thus there is reduced surface diffusion and hence enhanced electromigration lifetime. In case of the clad structure the failure time is nearly 38 times better than pure Ag and almost 7 times better than that of the alloy structure because of the reasons cited in the previous section. Thus it has been experimentally proven that the cladded Ag and Ag alloy structure shows better adhesion and electromigration resistance compared to pure Ag and can be thus proposed to be used as high temperature interconnect metallization.

While one or more specific preferred embodiments have been described application, those skilled in the art will readily recognize modifications, variations and equivalents that do not depart from the spirit and scope of the subject invention, as herein claimed. 

1. A process for the manufacture of conductive interconnects in semiconductor integrated circuits, devices and components comprising the steps of: (a) providing a Si surface; (b) growing a SiO2 layer on the Si surface; (c) depositing on the SiO2 layer a layer of Ag (Al) alloy containing Al in the range from about 0.5 atomic % to about 5 atomic % and Ag constituting substantially entirely the remainder of the alloy content; (d) depositing on the layer of Ag (Al) layer of step (c) a layer of Ag; and (e) depositing on the layer of Ag of step (d) a further layer of the Ag (Al) alloy.
 2. The process of claim 1, wherein step (c) comprises depositing the Ag (Al) alloy to a thickness sufficient to substantially reduce or eliminate reaction of the Ag layer of step (d) and the SiO2 layer of step (b).
 3. The process of claim 2, wherein step (c) comprises depositing the Ag (Al) alloy to a thickness of greater than about 6 nm.
 4. The process according to claim 3, wherein step (d) comprises depositing the Ag (Al) alloy to a thickness in excess of about 8 nm.
 5. The process according to claim 1, wherein step (e) comprising depositing the Ag (Al) alloy to a thickness sufficient to passivate the surface of the underlying Ag layer.
 6. The process according to claim 5, wherein step (e) comprises depositing the Ag (Al) alloy to a thickness in the range from about 3 nm to about 10 nm.
 7. The process according to claim 1, wherein the Ag (Al) alloy of steps (c) and (e) contains Al in the range greater than 0.5 atomic % to about 2 atomic %.
 8. The process according to claim 1, further comprising the step of removing native oxide from the Si surface prior to step (b).
 9. The process according to claim 1, wherein the torr depositions of steps (c), (d) and (e) are performed at a partial vacuum at below about 5×10⁻⁶ torr without breaking vacuum.
 10. The process according to claim 9, wherein the depositions of steps (c), (d) and (e) are by e-beam evaporation.
 11. A semiconductor device made by the process of claim
 1. 12. In an integrated circuit, component or device of the kind having a semiconductor substrate, an oxide layer, and integrated circuit components; the improvement comprising conductive clad silver interconnects comprising a layer of Ag between first and second layers of an alloy of Ag and Al comprising Ag and an Al content in a range from abut 0.5 atomic % to 5 atomic %.
 13. The integrated circuit, component or device according to claim 12, wherein the first layer of alloy separates the Ag and the oxide and has a thickness sufficient to substantially reduce or eliminate reaction of the Ag layer and the oxide.
 14. The integrated circuit, component or device according to claim 13, wherein the first layer of alloy has a thickness of greater than about 6 nm.
 15. The integrated circuit, component or device according to claim 13, wherein the second layer of Ag is deposited on the first alloy layer surface to a thickness in excess of about 8 nm.
 16. The integrated circuit, component or device according to claim 12, wherein the second layer of alloy is deposited on the Ag surface to a thickness sufficient to passivate the underlying Ag layer.
 17. The integrated circuit, component or device according to claim 16, wherein thickness of the second alloy layer is in the range from about 3 nm to about 10 nm.
 18. The integrated circuit, component or device according to claim 12, wherein the Ag (Al) alloy contains Al in the range greater than 0.5 atomic % to about 2 atomic %.
 19. A conductive metallized interconnect deposited on a substrate and having a structure comprising: (a) a first layer of an Ag (Al) alloy deposited upon the substrate, (b) a second layer of substantially pure Ag deposited on the first layer, and (c) a third layer of the Ag (Al) alloy deposited on the second layer.
 20. The conductive metallized interconnect according to claim 19, wherein the first layer has a thickness in a range from about 6 nm to about 12 nm, the second layer has a thickness in excess of about 8 nm and the third layer has a thickness in a range from about 3 nm to about 10 nm, the Ag (Al) alloy comprising Al content in a range from abut 0.5 atomic percent to about 5 atomic % and the remainder being substantially pure Ag. 